Traditional approaches for the design specification of computer hardware are based on either a netlist register transfer level (RTL) description or a functional hardware description. A functional description does not represent the detailed hardware layout with all interconnections and functional elements, but it is predominantly used to quickly provide a hardware specification which can be executed and examined or verified at the earliest development stage. Hereby the functional properties envisaged for the hardware are converted to functional features which are then linked together.
A functional specification can be set up in any programming language like `C` or `C++`, but often specifically modified languages like `BEHAVIOUR` are utilized to take particular hardware properties into account. After having been compiled for the target computer system, the functional specification can be used for the hardware simulation on a standard computer using an operating system like `UNIX` (operating system developed at Bell laboratories, registered trademark of UNIX system laboratories). The functional description approach therefore allows to present complex hardware structures in a manner that enables to detect hardware failures as early as possible in the design phase.
In contrast to the above functional approach, a netlist description, in any case, is necessary to get a hardware product for the design. The netlists can be described by particular hardware description languages like `DSL` (Hardware Design Language, developed at IBM development laboratory, Boeblingen, Germany) which is characterized by utilizing only one data structure namely bundles of conductors. Therefore, `DSL` requires only attribute declarations for Input/Output features or clock signals. Storage elements like registers and arrays are regarded as blocks. The vocabulary of that language embraces only operators with a low hardware complexity like logic operators `compare`, `if-then`, `add`, and `subtract`.
An other netlist description approach is `VHDL`, a programming language like `ADA`, which is extended by particular hardware operations. Accordingly, that language comprises a number of data structures and all statements of a common programming language like `loop` statements. By the provision of particular statements for timing and signalling, `VHDL` becomes a real hardware description language. One disadvantage of `VHDL` is that simulation is event driven due to the required signal definitions.
The prementioned description languages are rather different from the predescribed functional approach with regard to the respective underlying methodology. A simulation procedure based on the functional approach executes the complete hardware sequentially function by function. However, for each state transition, not all functions have to be executed since most of them exclude each other.
In contrast to that, in the netlist approach, the hardware is described in parallel whereby functional relationships become not evident. Therefore, in order to simulate a netlist, the netlist description has to be analyzed, sorted, and stored as a design model in a particular data structure. Thereafter a simulator engine can execute that design model. But the functional properties of the simulated hardware are entirely lost. Therefore that approach is rather time consuming. But at this time, no method exists which enables a simple or even automatic conversion from a functional description of hardware to a correct and complete netlist. Therefore, for all designs, expensive netlist specifications have to be generated and verified manually.
Further, the design of today's complex digital signal processing systems increasingly relies on sophisticated design tools for a functional analysis and simulation. Recent work has been concerned with the integration of such simulation tools, wherein data flow-oriented approaches have proven to be very well suited for both tasks due to the nature of most digital signal processing applications. Further known is the integration of control flow into data flow oriented simulation and syntheses.
Various state-machine development tools for high-level design entry and simulation are known in the art in order to shorten the design time and to ensure the correctness of the simulation results. For the analysis of a typical computer design, the sequential control logic of the hardware system realized as finite state machines is one of the major design efforts.
An other major problem which is addressed e.g. in an article by A. Aziz et al. published in IEEE Computer Society Press, Los Alamitos, USA, and entitled "Minimizing Interacting Finite State Machines: A Compositional Approach to Language Containment", is compositional minimization of collections of interacting finite state machines that arise in the context of formal verification of hardware designs. It is recognized by the authors that much of the behavior of a designed system is redundant with respect to a given property being verified, and so the system can be replaced by substantially simpler representations. The authors show that these redundancies can be captured by computing states that are input-output equivalent in the presence of fairness. Since computing complete equivalences is computationally expensive, they further propose a spectrum of approximations which are efficiently computable. For instance, procedures are described that hierarchically minimize the system with respect to explicit representations.
Thereupon, a number of approaches in the field of translation of data flow information into a hardware description language are known. In an article by W. H. Chou and S. Y. Kung published in IEEE Computer Society Press, Los Alamitos, USA, and entitled "Register Transfer Modelling and Simulation for Array Processors", a register transfer modelling scheme is described where a data flow graph of the design is translated into a register transfer language which is further combined with a hardware description module. Hereby an interactive simulator is implemented to simulate the behavior of such a system.
Further, in an article by A. D. Gordon, published in IEEE Computer Society Press, Los Alamitos, USA, and entitled "The Formal Definition of a Synchronous Hardware-Description", a hardware verification method is described which provides connections between a language used in practice to design a circuit and an other language which is used for research into hardware verification. Hereby a simple data flow language is used for specifying digital signal processing circuits wherein a higher-order logic is extensively used for research into hardware verification. Particular, a combination of operational and predictive semantics is used to define formally a substantial subset of the data flow language by mapping that language definitions into the high-order logic predicates.
An other high-level hardware design environment is disclosed in an article by F. Rocheteau and N. Halbwachs published in Elsevier, Amsterdam, Netherlands, in 1992 and entitled "POLLUX: LUSTRE BASED HARDWARE DESIGNED ENVIRONMENT". Hereby a design description is written in a data-flow language, and used by a different tool to produce the corresponding synchronous circuit or a simulation program that can be compiled and executed on a sequential machine.
Beyond the above approaches, also object-oriented concepts for hardware description languages are already known, for instance, from an article by A. J. Van der Hoeven et al. published in IEEE Computer Society Press, Los Alamitos, USA, and entitled "A Hardware Designed System Based on Object-Oriented Principles". Most hardware description languages and their environments are either based on imperative language concepts or on functional language concepts. The hardware specification and simulation environment described in that article is based on object-oriented concepts such as classes, objects, inheritance, and abstraction. The underlying hardware design model uses also applicative state transitions to describe the functionality and data flow of a VLSI network.
A further object-oriented approach is disclosed in IBM TDB No. 12, 5/91, pages 435-436 entitled "State Machine Verification Expert". That expert system is conceived for generating all possible scenarios for a state-machine. The state-machine is described in the form of knowledge-based entities, wherein state transition rules are represented as forward-chaining rules. The system particularly provides a natural representation of the state-machine and uses some heuristic and causal knowledge to prune the surge space of the inputs and the state. Thus, it is possible for the expert system to test effectively all the combinations of the input signals and the possible states of the state-machine in a reasonable time. The described knowledge-based concept has the advantage that it can generate explanations for the behavior of the machine as time evolves, and it can mask out the details at a low level of operation of the machine to generate output only at a higher level. The object-oriented approach provides a classification of the data structures into hierarchies of units that represent an entity in the state-machine. The expert system generates a function that looks at the possible values of the control inputs and tries all possible combinations for the rules to filter through and generate scenarios.
Beyond the above approaches, from U.S. Pat. No. 5,369,594 an improved circuit design system and method is known. The circuit under simulation which may have both passive and active linear and non-linear elements is partitioned into sub-circuits such that some sub-circuits contain only linear elements. By this technique, simulation of large circuits containing large areas of passive components, the overall time for simulation is significantly reduced.
An other design method for the implementation of data-flow partitions in a high-level design of a chip making use of growable logical macrofunction library to describe data-flow and control logic partitions is disclosed in EP Application No. 91.480.167.5. That design method comprises a logic entry step to capture with a high-level language the design of the chip, making use of the logical macrofunction library to describe data-flow control logic partitions, a high-level logic simulation step using word model data that represent the logic behavior of the macrofunctions to simulate at high-level the behavior of the high-level logic, a structure extraction step to extract the pertinent physical data from the high-level logic using a word map that describes the physical placement of books within the macrofunctions and the logical models of the books, a book level logic verification step to make sure that the book level logic is consistent with the high-level logic, and besides other steps, a power assignment step using the book level logic to set up the correct level of power of the books contained in the book level logic.
Further, in an article published in IBM Technical Disclosure Bulletin (TDB) Volume 38 No. 7, 1995, pages 253-254, entitled "Method to Analyze Global Transient Phenomena Induced by Changes in the State of Very Large Simulation Models", an event simulator approach is described for a global analysis of a Central Processing Unit (CPU). The particular problems addressed there are long CPU run times and the analysis of transient variables like power, local heating, changes in power supply currents, voltage shifts on power supply busses, noise induced logic changes and noise induced analog circuit errors. The basic concept of that approach is to do an abstraction of what the design does at each state change.
An enhanced functional simulator to verify technology independent logic is described in IBM TDB No. 2, 7/91, pages 252-253, entitled "Hardware Cycle Simulation Coverage Measurement Tool". The analysis of the logic is based on a data flow analysis which checks how the logic BOOLEAN values are propagated and which verifies that latches and busses have correct values at specific times. Further a control flow analysis checks the sequences of switches and decision elements that lead to a logic state change. It verifies whether or not they have been activated during the simulation. In particular, a program is described which quantifies logic control flow activation during the simulation phase and thus permits validating the test case coverage.
A static flow analysis logic design is described in IBM TDB No.8, 1/91, pages 437-441. By means of a logic synthesis, conversion of a functional level hardware specification into a logic gate-level realization is performed. The logic synthesis system is used to convert the model to a basic design language for structure language representation. This gate-level representation allows for timing analysis to be done on the function. The hardware design cycle used to produce the chips starts with high-level functional specifications, timing requirements, and data-flow diagrams. Once these are complete, a software model of the functions is created using the basic design language. It is run through various timing analysis programs to verify that the timing of the hardware design is correct. Once both the function and the timing are verified, the logic design is complete. In a following step the physical design of the chip, i.e. the placement and wiring, is addressed. Finally, the chip is actually fabricated, tested, and returned to the logic designers.
A hardware design development system where the logic under simulation is partitioned into several functional islands which are developed in parallel is described in IBM TDB No. 7, 12/90, pages 247-251 entitled "Multi-Clock Rate Device for Hardware Simulation Efficiency Improvement". The simulation begins on isolated islands, than goes up with larger and larger structures to reach functions grouping different cards of a future machine. All the islands are not ready to be connected at the same time since many of problems occur on interfaces between these islands. Thus, at the beginning of a simulation project, simulation devices are defined that represent subsets of functions of different interfaces to allow the designers to simulate their logic before really interfaces are available.
An enhanced functional simulator which efficiently converts a parallel hardware description to a serial description for logic simulation, is disclosed in IBM TDB No. 11, 4/90, pages 354-361, entitled "Model Ordering for Compiled Enhanced Functional Simulator". Hardware models which are going to be simulated by a logic simulator, are segmented into clock sections. Each clock section is further broken into a signal block section and latch block section. Register transfer language statements are assigned to the slowest clock section possible that will still give correct behavior.
A simulation program which simulates dynamic performance of a large set of interconnected circuits is described in IBM TDB 2/73, pages 2973-2975. A design description is contained in a block using simulation library information to develop a simulation data base. The block uses well-known small signal circuit analysis techniques to develop equivalent circuits and netlists describing the circuit logic to be simulated. The output of the block provides the simulation data base which is formatted for efficient processing by a simulation algorithm. In particular, the simulation time is divided into discrete steps. The simulation algorithm treats individual logic circuits independently during a time step, because the time step is small compared to circuit transition times. During any one time step, only those circuits which might have a change in a state variable are simulated. Those circuits clearly quiescent are not simulated. The computation of the circuit responds for all of the individual logic circuits is performed serially by circuit for a single time step. Inputs to all circuits make use of the results just computed and any external signal changes during this time step. After all circuits have been analyzed, the results are placed in an event file and the time is incremented.